SI5328 Datasheet, PDF (61/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Pin # Pin Name I/O Signal Level
Description
26
A2_SS
I
LVCMOS Serial Port Address/Slave Select.
In I²C control mode (CMODE = 0), this pin functions as a hardware
controlled address bit [A2].
In SPI control mode (CMODE = 1), this pin functions as the slave
select input.
This pin has a weak pull-down.
27
SDI
I
LVCMOS Serial Data In.
In I²C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the serial
data input.
This pin has a weak pull-down.
29 CKOUT1– O
28 CKOUT1+
Multi
Output Clock 1.
Differential output clock with a frequency range of 8 kHz to
808 MHz. Output signal format is selected by SFOUT1_REG regis-
ter bits. Output is differential for LVPECL, LVDS, and CML compati-
ble modes. For CMOS format, both output pins drive identical
single-ended clock outputs.
34 CKOUT2– O
35 CKOUT2+
Multi
Output Clock 2.
Differential output clock with a frequency range of 8 kHz to
808 MHz. Output signal format is selected by SFOUT2_REG regis-
ter bits. Output is differential for LVPECL, LVDS, and CML compati-
ble modes. For CMOS format, both output pins drive identical
single-ended clock outputs.
36
CMODE I
LVCMOS Control Mode.
Selects I²C or SPI control mode.
0 = I²C Control Mode
1 = SPI Control Mode
This pin must not be NC. Tie either high or low.
See the Si53xx Family Reference Manual for details on I²C or SPI
operation.
GND PAD
GND
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
Rev. 1.0
61