SI5328 Datasheet, PDF (29/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 8.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
HLOG_2[1:0]
HLOG_1[1:0]
Reserved
Type
R/W
R/W
R
Reset value = 0000 0000
Bit
Name
Function
7:6 HLOG_2 [1:0] HLOG_2 [1:0].
00: Normal operation
01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
5:4
HLOG_1 [1:0].
00: Normal operation
01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
3:0 Reserved Reserved.
Register 9.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
HIST_AVG [4:0]
Reserved
Type
R/W
R
R
R
Reset value = 1100 0000
Bit
Name
Function
7:3 HIST_AVG [4:0] HIST_AVG [4:0].
Selects amount of averaging time to be used in generating the history information for
Digital Hold.
See the Si53xx Family Reference Manual for a detailed description
2:0
Reserved Reserved.
Rev. 1.0
29