SI5328 Datasheet, PDF (17/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
3. Typical Application Circuit
Note: For an example schematic and layout, refer to the Si5328-EVB User’s Guide.
V_DD = 3.3 V
System
Power
Supply
Ferrite
Bead
130 
82 
130 
82 
CKIN1+
CKIN1–
C₄ 1 µF
C₁ 0.1 µF
C₂ 0.1 µF
C3 0.1 µF
CKOUT1+
CKOUT1–
Input
Clock
Sources*
VDD = 3.3 V
130 
82 
130 
82 
CKIN2+
CKIN2–
CKOUT2+
CKOUT2–
Si5328
INT_C1B
C2B
Ref Clk Rate
V_DD
15 k
15 k
RATE[1:0]²
Refclk+
Refclk–
0.1 µF
XA
0.1 µF
XB
Control Mode (L)
Reset
CMODE
RST
LOL
A[2:0]
SDA
SCL
CS_CA
0.1 µF
+
100 
–
0.1 µF
0.1 µF
+
100 
–
0.1 µF
Clock Outputs
Interrupt/CKIN1 Invalid Indicator
CKIN2 Invalid Indicator
PLL Loss of Lock Indicator
Serial Port Address
Serial Data
I²C Interface
Serial Clock
Clock Select/Clock Active
Notes:
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground),
M (VDD/2), and H (VDD).
3. I²C-required pull-up resistors not shown.
Figure 4. Si5328 Typical Application Circuit (I²C Control Mode)
Rev. 1.0
17