SI5328 Datasheet, PDF (11/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Table 3. AC Characteristics (Continued)
(V_DD = 2.5 ±10% or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
PLL Performance
(fin = fout = 346 MHz; BW = 0.088 Hz; LVPECL)
Lock Time¹
t_LOCKMP Start of ICAL to LOL low,
—
LOCKT = 4, FASTLOCK
enabled
Settle Time¹
Start of ICAL to LOL low,
—
LOCKT = 1, FASTLOCK
enabled
t_SETTLE
Start of ICAL to output
—
phase within 45 degrees of
final value, LOCKT = 4,
FASTLOCK enabled
Start of ICAL to output
—
phase within 45 degrees of
final value, LOCKT = 1,
FASTLOCK enabled
Output Clock Phase
t_{P_STEP}
After clock switch
—
Change
f3  128 kHz
Closed Loop Jitter
Peaking
Jitter/Wander
Tolerance²
J_PK
J_TOL
—
Jitter Frequency Loop 5000/BW
Bandwidth
Phase Noise
fout = 156.25 MHz
1 kHz Offset
—
10 kHz Offset
—
CKO_PN
100 kHz Offset
—
Typ
2
12.5
1
1
200
0.05
—
–120
–128
–130
Max
Unit
—
s
—
s
—
s
—
s
—
ps
0.2
dB
—
ns pk-pk
—
dBc/Hz
—
dBc/Hz
—
dBc/Hz
1 MHz Offset
—
–144
—
dBc/Hz
Subharmonic Noise
SP_SUBH Phase Noise @ 100 kHz
—
–88
—
dBc
Offset
Spurious Noise
SP_SPUR
Max spur @ n x F3
—
–93
—
dBc
(n  1, n x F3 < 100 MHz)
Notes:
1. Lock and settle times may change with different f3, loop BW, and VCO frequency values. Contact Silicon Labs for
further details.
2. See Section 9 of “AN775: Si5328 Synchronous Ethernet Compliance Test Report” for more details.
Rev. 1.0
11