SI5328 Datasheet, PDF (28/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 7.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Reserved
FOSREFSEL [2:0]
Type
R
R/W
Reset value = 0010 1010
Bit
Name
Function
7:3
Reserved.
Reserved.
2:0 FOSREFSEL [2:0] FOSREFSEL [2:0].
Selects which input clock is used as the reference frequency for frequency offset
(FOS) alarms.
000: XA/XB (External reference)
001: CKIN1
010: CKIN2
011: Reserved
100: Reserved
101: Reserved
110: Reserved
111: Reserved
28
Rev. 1.0