SI5328 Datasheet, PDF (64/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
9. Package Outline: 36-Pin QFN
Figure 7 illustrates the package details for the Si5328. Table 12 lists the values for the dimensions shown in the
illustration.
Figure 7. 36-Pin Quad Flat No-lead (QFN)
Table 12. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
6.00 BSC
D2
3.95
4.10
4.25
e
0.50 BSC
E
6.00 BSC
E2
3.95
4.10
4.25
Min
Nom
Max
L
0.50
0.60
0.70

—
—
12º
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
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Rev. 1.0