SI5328 Datasheet, PDF (19/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

4. Functional Description
Si5328
TCXO or Refclock
CKIN1
CKIN2
÷ N31
÷ N32
Refclock
Hitless Switching
Mux
DSPLL^®
÷ N2
÷ N1_HS
÷ N1_LS
÷ N2_LS
CKOUT1
CKOUT2
Loss of Signal/
Frequency Offset
Loss of Lock
Signal Detect
Control
VDD (2.5 or 3.3 V)
GND
I²C/SPI Port
Device Interrupt
Rate Select
Clock Select
Figure 6. Functional Block Diagram
The Si5328 is a jitter-attenuating precision clock
multiplier for Synchronous Ethernet applications
requiring sub 1 ps jitter performance and ultra-low loop
bandwidth. When combined with a low-wander
reference oscillator, the Si5328 meets all of the wander,
MTIE, TDEV, and other requirements that are listed in
ITU-T G.8262/Y.1362. The Si5328 accepts two input
clocks ranging from 8 kHz to 710 MHz and generates
two output clocks ranging from 8 kHz to 808 MHz. The
Si5328 can also use its TCXO as a clock source for
frequency synthesis. The device provides virtually any
frequency translation combination across this operating
range. Independent dividers are available for each input
clock and output clock, so the Si5328 can accept input
clocks at different frequencies and it can generate
output clocks at different frequencies. The Si5328 input
clock frequency and clock multiplication ratio are
programmable through an I²C or SPI interface. Silicon
Laboratories offers a PC-based software utility,
DSPLLsim, that can be used to determine the optimum
PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase
noise and power consumption. This utility can be
downloaded from http://www.silabs.com/timing.
The Si5328 is based on Silicon Laboratories' 3rd-
generation DSPLL^® technology, which provides any
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The Si5328
PLL loop bandwidth is digitally programmable and
supports a range from less than 0.1 Hz to 6 Hz. The
DSPLLsim software utility can be used to calculate valid
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.
The Si5328 supports hitless switching between the two
synchronous input clocks in compliance with G.8262
that greatly minimizes the propagation of phase
transients to the clock outputs during an input clock
transition (maximum 200 ps phase transient). Manual
and automatic revertive and non-revertive input clock
switching options are available. The Si5328 monitors
both input clocks for loss-of-signal (LOS) and provides a
LOS alarm (INT_C1B and C2B) when it detects missing
pulses on either input clock. The device monitors the
lock status of the PLL. The lock detect algorithm works
by continuously monitoring the phase of the input clock
in relation to the phase of the feedback clock. The
Si5328 also monitors frequency offset alarms (FOS),
which indicate if an input clock is within a specified
frequency band relative to the frequency of a reference
clock. Both Stratum 3/3E and SONET Minimum Clock
(SMC) FOS thresholds are supported.The Si5328
provides a digital hold capability that allows the device
to continue generation of a stable output clock when the
selected input reference is lost. During digital hold, the
DSPLL generates an output frequency based on a
historical average frequency that existed for a fixed
amount of time before the error event occurred,
eliminating the effects of phase and frequency
transients that may occur immediately preceding digital
hold.
The Si5328 has two differential clock outputs. The
electrical format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or
CMOS loads. If not required, the second clock output
can be powered down to minimize power consumption.
Rev. 1.0
19