SI5328 Datasheet, PDF(10/70 Page) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

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SI5328 Datasheet, PDF (10/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

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Si5328

Table 3. AC Characteristics (Continued)

(VDD = 2.5 Â±10% or 3.3 V Â±10%, TA = â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Rise/Fall

(20â80%) @

CKOTRF LVPECL, LVDS or CML

230

350

Output

312.5 MHz output

Output Duty Cycle

Uncertainty @

CKODC

100 ï Load

Line-to-Line

808 MHz

Measured at 50% Point

(Not for CMOS)

LVCMOS Input Pins

Minimum Reset Pulse

Width

Reset to Microproces-

sor Access Ready

Input Capacitance

LVCMOS Output Pins

tRSTMN

tREADY

Cin

Âµs

Rise/Fall Times

tRF

CLOAD = 20pf

See Figure 2

LOSn Trigger Window LOSTRIG From last CKINn ïï to ï¯

Internal detection of LOSn

N3 â 1

Time to Clear LOL

tCLRLOL

ï¯LOS to ï¯LOL

after LOS Cleared

Fold = Fnew

Stable Xa/XB reference

Device Skew

4.5 x N3 TCKIN

Output Clock Skew

tSKEW

ï of CKOUTn to ï of

100

CKOUT_m, CKOUTn

and CKOUT_m at same

frequency and signal

format

PHASEOFFSET = 0

CKOUT_ALWAYS_ON = 1

SQ_ICAL = 1

Phase Change due to

tTEMP Max phase changes from â

300

500

Temperature Variation

40 to +85 Â°C, stable XAXB

reference

Notes:

1. Lock and settle times may change with different f3, loop BW, and VCO frequency values. Contact Silicon Labs for

further details.

2. See Section 9 of âAN775: Si5328 Synchronous Ethernet Compliance Test Reportâ for more details.

Rev. 1.0

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