SI5328 Datasheet, PDF (1/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
I T U - T G. 8 2 6 2 S YNCHRONOUS E THERNET J ITTER- A TTENUATING
CLOCK MULTIPLIER
Features
 Fully-compliant with ITU-T
G.8262, EEC options 1 and 2.
 Generates any frequency from
8 kHz to 808 MHz.
 Dual clock outputs with
selectable signal format
(LVPECL, LVDS, CML, CMOS)
 LOL, LOS, FOS alarm outputs
 Ultra-low jitter clock outputs with _{ I}²_{C or SPI programmable}
jitter generation as low as 0.3 ps _{ On-chip voltage regulator for}
rms (12 kHz–20 MHz)
2.5 ±10% or 3.3 V ±10%
 Integrated loop filter with
operation
selectable loop bandwidth
(0.1 Hz; 1 to 10 Hz)
 Small size: 6 x 6 mm 36-lead
QFN
 Dual clock inputs with manual or _{ Pb-free, ROHS compliant}
automatically controlled hitless
switching
Applications
 G.8262 Synchronous Ethernet,
EEC options 1 and 2
 GbE/10GbE/100GbE
Synchronous Ethernet
 Carrier Ethernet switches,
routers
Description
The Si5328 is a jitter-attenuating precision clock multiplier for
Synchronous Ethernet applications requiring sub 1 ps jitter performance
and ultra-low loop bandwidth. When combined with a low-wander, low-
jitter reference oscillator, the Si5328 meets all of the wander, MTIE,
TDEV, and other requirements listed in ITU-T G.8262/Y.1362. The Si5328
accepts two input clocks ranging from 8 kHz to 710 MHz and generates
two output clocks ranging from 8 kHz to 808 MHz. The two outputs are
divided down separately from a common source. The Si5328 can also
use the TCXO as a clock source for frequency synthesis. The device
provides virtually any frequency translation combination across this
operating range. The Si5328 input clock frequency and clock
multiplication ratio are programmable through an I²C or SPI interface. The
Si5328 is based on Silicon Laboratories' third-generation DSPLL^®
technology, which provides frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need for external VCXO
and loop filter components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at the application
level. Operating from a single 2.5 or 3.3 V supply, the Si5328 is ideal for
providing clock multiplication and jitter attenuation in high-performance,
Synchronous Ethernet timing applications.
Ordering Information:
See page 63.
Pin Assignments
36 35 34 33 32 31 30 29 28
RST 1
27 SDI
NC 2
26 A2_SS
INT_C1B 3
25 A1
C2B 4
VDD 5
XA 6
GND
Pad
24 A0
23 SDA_SDO
22 SCL
XB 7
21 CS_CA
GND 8
20 NC
NC 9
19 NC
10 11 12 13 14 15 16 17 18
Rev. 1.0 7/13
Copyright © 2013 by Silicon Laboratories
Si5328