SI5341 Datasheet, PDF (8/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 3. Input Specifications
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Units
Input Differential Voltage Swing V_{IN_DIFF}
365
—
2500 mVpp_diff
Slew rate^{1, 2}
SR Imposed for best jitter per- 400
—
—
V/µs
formance
Input Duty Cycle
DC
40
—
60
%
Notes:
1. Imposed for jitter performance.
2. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20 = ((0.8 - 0.2) * V_{IN_Vpp_se}) / SR.
3. V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD.
4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended
LVCMOS inputs to IN0,1,2 it is required to ac-couple into the differential input buffer.
5. Voltage swing is specified as single-ended mVpp.
6. Contact Silicon Labs Technical Support for more details.
Table 4. Control Input Pin Specifications
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, V_DDS = 3.3 V ±5%, 1.8 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Units
Si5341 Control Input Pins
(I2C_SEL, IN_SEL[1:0], RST, OE, SYNC, A1, SCLK, A0/CS, FINC, FDEC, SDA/SDIO)
Input Voltage
Input Capacitance
Input Resistance
Minimum Pulse Width
V_IL
—
— 0.3xV_DDIO*
V
V_IH
0.7xV_DDIO* —
—
V
C_IN
—
2
—
pF
R_IN
—
20
—
k
T_PW
RST, SYNC,
100
—
—
ns
FINC, and FDEC
Frequency Update Rate
F_UR FINC and FDEC
—
—
1
MHz
Si5340 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, A1, SDA, SDI, SCLK, A0/CS, SDA/SDIO)
Input Voltage
V_IL
—
— 0.3xV_DDIO*
V
V_IH
0.7xV_DDIO* —
—
V
Input Capacitance
C_IN
—
2
—
pF
Input Resistance
R_IN
—
20
—
k
Minimum Pulse Width
T_PW
RST only
100
—
—
ns
*Note: V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD. Refer to the Reference Manual for more
details on register settings.
8
Rev. 1.0