SI5341 Datasheet, PDF (40/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 17. High-Level Register Map (Continued)
16-Bit Address
8-bit Page
Address
8-bit Register
Address Range
02
01
Content
Set Page Address
02–05
08–2F
30
XTAL Frequency Adjust
Input Divider (P) Settings
Input Divider (P) Update Bits
35–3D
PLL Feedback Divider (M) Settings
3E
PLL Feedback Divider (M) Update Bit
47–6A
Output Divider (R) Settings
6B–72
FE
03
01
User Scratch Pad Memory
Device Ready Status
Set Page Address
02–37
MultiSynth Divider (N0–N4) Settings
0C
MultiSynth Divider (N0) Update Bit
17
MultiSynth Divider (N1) Update Bit
22
MultiSynth Divider (N2) Update Bit
2D
MultiSynth Divider (N3) Update Bit
38
MultiSynth Divider (N4) Update Bit
39–58
FINC/FDEC Settings N0–N4
59–62
63–94
Output Delay (t) Settings
Frequency Readback N0–N4
04–08
09
FE
00–FF
01
49
Device Ready Status
Reserved
Set Page Address
Input Settings
1C
Zero Delay Mode Settings
A0–FF
00–FF
Reserved
40
Rev. 1.0