SI5341 Datasheet, PDF (30/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
DifferentialConnection
nc ^X1
nc ^X2
2xCL
0.1 uf
XA
OSC
XB
2xCL
0.1 uf
Note: 2.5 Vpp diff max
Si5341/40
Single‐ended XO Connection
nc ^X1
nc ^X2
Note: 2.0 Vpp_se max
2xCL
0.1 uf
XA
OSC
XO with Clipped Sine Wave _{0.1 uf} ^XB
Output
2xCL
Si5341/40
CMOS Output
XO VDD
3.3 V
2.5 V
1.8 V
R1
523 
475 
158 
R2
442 
649 
866 
Single‐ended Connection
nc ^X1
nc ^X2
Note: 2.0 Vpp_se max
2xCL
R1
0.1 uf
XA
OSC
R2
0.1 uf
0.1 uf ^XB
2xCL
Si5341/40
Crystal Connection
X1
XA
XTAL
XB
X2
2xCL
OSC
2xCL
Si5341/40
Figure 11. XAXB External Crystal and Clock Connections
5.3.2. Input Clocks (IN0, IN1, IN2)
A differential or single-ended clock can be applied at IN2, IN1, or IN0. The recommended input termination
schemes are shown in Figure 12.
Differential
Driver LVDS,
LVPECL, CML
AC Coupled Differential
0.1 uf
50
0.1 uf
50
INx
50
INx
50
0.1 uf
Si5341/40
AC Coupled LVCMOS or Single Ended
3.3V, 2.5V, 1.8V
LVCMOS or Single
Ended Signal
50
0.1 uf
Si5341/40
INx
0.1 uf INx
Figure 12. Termination of Differential and LVCMOS Input Signals
30
Rev. 1.0