SI5341 Datasheet, PDF (16/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 9. I²C Timing Specifications (SCL,SDA)
Parameter Symbol Test Condition
SCL Clock
f_SCL
Frequency
Hold Time
(Repeated)
START Condition
t_HD:STA
Low Period of the
SCL Clock
t_LOW
HIGH Period of
the SCL Clock
t_HIGH
Set-up Time for a
Repeated START
Condition
t_SU:STA
Data Hold Time
Data Set-up Time
Rise Time of Both
SDA and SCL
Signals
t_HD:DAT
t_SU:DAT
t_r
Fall Time of Both
t_f
SDA and SCL
Signals
Set-up Time for
STOP Condition
t_SU:STO
Bus Free Time
t_BUF
between a STOP
and START Con-
dition
Data Valid Time
Data Valid
Acknowledge
Time
t_VD:DAT
t_VD:ACK
Min
Max
Standard Mode
100 kbps
—
100
4.0
—
4.7
—
4.0
—
4.7
—
100
—
250
—
—
1000
—
300
4.0
—
4.7
—
—
3.45
—
3.45
Min
Max
Fast Mode
400 kbps
—
400
0.6
—
Units
kHz
µs
1.3
—
µs
0.6
—
µs
0.6
—
µs
100
—
ns
100
—
ns
20
300
ns
—
300
ns
0.6
—
µs
1.3
—
µs
—
0.9
µs
—
0.9
µs
16
Rev. 1.0