SI5341 Datasheet, PDF(6/56 Page) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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SI5341 Datasheet, PDF (6/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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Si5341/40

Table 2. DC Characteristics

(VDD = 1.8 V Â±5%, VDDA = 3.3 V Â±5%, VDDO = 1.8 V Â±5%, 2.5 V Â±5%, or 3.3 V Â±5%, TA = â40 to 85 Â°C)

Parameter

Core Supply Current

Output Buffer Supply Current

Total Power Dissipation

Symbol

IDD

IDDA

IDDOx

Test Condition

Si5341

Note 1

Si5340

Note 2

Min Typ Max Units

100 150

130

Si5341

Note 1

115 125

Si5340

Note 2

115 125

LVPECL Output3

@ 156.25 MHz

LVDS Output3

@ 156.25 MHz

3.3 V LVCMOS4 output â

@ 156.25 MHz

2.5 V LVCMOS4 output â

@ 156.25 MHz

1.8 V LVCMOS4 output â

@ 156.25 MHz

Si5341

Notes 1,5

830 980

Si5340

Notes 2,5

685 815

Notes:

1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.

2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.

3. Differential outputs terminated into an ac-coupled 100 ïï load.

4. LVCMOS outputs measured into a 6-inch 50 ï PCB trace with 5 pF load. The LVCMOS outputs were set to

OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5341/40 Family Reference Manual for more

details on register settings.

Differential Output Test Configuration

LVCMOS Output Test Configuration

IDDO

OUT

0.1 uF

100

0.1 uF

IDDO

OUTa

OUTb

6 inch

5 pF

5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board

(EVB) is not available. All EVBs support detailed current measurements for any configuration.

Rev. 1.0

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