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| SI5341 Datasheet, PDF (35/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR | |||
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Si5341/40
5.5.12. Output Delay Control (ït0 â ït4)
The Si5341/40 uses independent MultiSynth dividers (N0 - N4) to generate up to 5 unique frequencies to its 10
outputs through a crosspoint switch. By default all clocks are phase aligned. A delay path (ït0 - ït4) associated with
each of these dividers is available for applications that need a specific output skew configuration. Each delay path
is controlled by a register parameter call Nx_DELAY with a resolution of ~0.28 ps over a range of ~±9.14 ns. This is
useful for PCB trace length mismatch compensation. After the delay controls are configured, the soft reset bit
SOFT_RST must be set high so that the output delay takes effect and the outputs are re-aligned.
÷N0 t0
÷N1 t1
÷N2 t2
÷N3 t3
÷N4 t4
÷R0
÷R1
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
÷R8
÷R9
VDDO0
OUT0
OUT0
VDDO1
OUT1
OUT1
VDDO2
OUT2
OUT2
VDDO3
OUT3
OUT3
VDDO4
OUT4
OUT4
VDDO5
OUT5
OUT5
VDDO6
OUT6
OUT6
VDDO7
OUT7
OUT7
VDDO8
OUT8
OUT8
VDDO9
OUT9
OUT9
Figure 16. Example of Independently Configurable Path Delays
All delay values are restored to their NVM programmed values after power-up or after a hard reset. Delay default
values can be written to the NVM allowing a custom delay offset configuration at power-up or after a hardware
reset.
Rev. 1.0
35
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