SI5341 Datasheet, PDF (26/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
4. Detailed Block Diagrams
IN_SEL[1:0]
IN0
IN0
IN1
IN1
IN2
IN2
3
÷P₀
÷P₁
÷P₂
25MHz,
XB
48-54MHz
XTAL
XA
FB_IN
FB_IN
÷ PXAXB
OSC
Zero Delay
Mode
÷P_fb
I2C_SEL
SDA/SDIO
A1/SDO
SCLK
A0/CS
SPI/
I²C
NVM
Status
Monitors
Si5341
Clock
Generator
PLL
PD
÷
M_n
M_d
LPF
MultiSynth
÷
N_0n
N_0d
t₀
÷
N_1n
N_1d
t₁
÷
N_2n
N_2d
t₂
÷
N_3n
N_3d
t₃
÷
N_4n
N_4d
t₄
Frequency
Control
Dividers/
Drivers
÷R₀
÷R₁
÷R₂
÷R₃
÷R₄
÷R₅
÷R₆
÷R₇
÷R₈
÷R₉
VDDO0
OUT0
OUT0
VDDO1
OUT1
OUT1
VDDO2
OUT2
OUT2
VDDO3
OUT3
OUT3
VDDO4
OUT4
OUT4
VDDO5
OUT5
OUT5
VDDO6
OUT6
OUT6
VDDO7
OUT7
OUT7
VDDO8
OUT8
OUT8
VDDO9
OUT9
OUT9
Figure 8. Si5341 Block Diagram
26
Rev. 1.0