SI5341 Datasheet, PDF (28/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
5. Functional Description
The Si5341/40 combines a wide band PLL with next generation MultiSynth technology to offer the industry’s most
versatile and high performance clock generator. The PLL locks to either an external crystal between XA/XB or to
an external clock connected to XA/XB or IN0,1,2. A fractional or integer multiplier takes the selected input clock or
crystal frequency up to a very high frequency that is then divided by the MultiSynth output stage to any frequency in
the range of 100 Hz to 712.5 MHz on each output. The MultiSynth stage can divide by both integer and fractional
values.The high-resolution fractional MultiSynth dividers enables true any-frequency input to any-frequency on any
of the outputs. The output drivers offer flexible output formats which are independently configurable on each of the
outputs. This clock generator is fully configurable via its serial interface (I²C/SPI) and includes in-circuit
programmable non-volatile memory.
5.1. Power-up and Initialization
Once power is applied, the device begins an initialization period where it downloads default register values and
configuration data from NVM and performs other initialization tasks. Communicating with the device through the
serial interface is possible once this initialization period is complete. No clocks will be generated until the
initialization is done. There are two types of resets available. A hard reset is functionally similar to a device power-
up. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state
including the serial interface. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft
reset bypasses the NVM download. It is simply used to initiate register configuration changes.
Power-Up
Hard Reset
bit asserted
RST
pin asserted
NVM download
Initialization
Soft Reset
bit asserted
Serial interface
ready
Figure 10. Si5341 Power-up and Initialization
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Rev. 1.0