SI5341 Datasheet, PDF (12/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 7. LVCMOS Clock Output Specifications
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Units
Output Frequency
0.0001 — 250 MHz
Duty Cycle
DC
Output-to-Output Skew
T_SK
Output Voltage High^{1, 2, 3} V_OH
f_OUT < 100 MHz
100 MHz < f_OUT < 250 MHz
47
—
53
%
44
—
55
—
— 100 ps
V_DDO = 3.3 V
OUTx_CMOS_DRV=1
I_{OH =} –10 mA V_DDO x —
—
V
OUTx_CMOS_DRV=2
I_{OH =} –12 mA
0.75
—
—
OUTx_CMOS_DRV=3
I_{OH =} –17 mA
——
V_DDO = 2.5 V
OUTx_CMOS_DRV=1
I_{OH =} –6 mA V_DDO x —
—
V
OUTx_CMOS_DRV=2
I_{OH =} –8 mA
0.75 _—
—
OUTx_CMOS_DRV=3
I_{OH =} –11 mA
——
V_DDO = 1.8 V
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
I_{OH =} –4 mA V_DDO x —
—
I_{OH =} –5 mA
0.75 _—
—
V
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer
to the Reference Manual for more details on register settings.
2. I_OL/I_OH is measured at V_OL/V_OH as shown in the dc test configuration.
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50  PCB trace. A 5 pF
capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
DC Test Configuration
Zs
V_OL/V_OH
I_OL/I_OH
IDDO
OUT
OUT
AC Test Configuration
Trace length 5 inches
499 
0.1 uF
50 
4.7 pF
56 
50 probe, scope
50 
499 
4.7 pF
0.1 uF
56 
50 probe, scope
12
Rev. 1.0