SI5341 Datasheet, PDF (14/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 8. Performance Characteristics
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
V_CO Frequency Range
PLL Loop Bandwidth
Initial Start-Up Time
POR¹ to Serial Interface
Ready
PLL Lock Time⁶
Output Delay Adjustment
Jitter Generation
Locked to External Clock²
Symbol
F_VCO
f_BW
t_START
t_RDY
Test Condition
Time from power-up to when the
device generates clocks (Input
Frequency > 48 MHz)
t_ACQ
t_{DELAY_-}
frac
t_{DELAY_int}
t_RANGE
J_GEN
f_IN = 19.44 MHz
f_VCO = 14 GHz
Delay is controlled by the Multi-
Synth
Integer Mode³
12 kHz to 20 MHz
Fractional/DCO Mode⁴
12 kHz to 20 MHz
J_PER
J_CC
J_PER
J_CC
Derived from
integrated phase noise
N = 10,000 cycles
Integer or Fractional Mode^3,4.
Measured in the time domain.
Performance is limited by the
noise floor of the
equipment.
Min
13.5
—
—
—
22
—
—
—
—
—
—
—
—
—
Typ Max
— 14.256
1.0
—
30
45
—
15
— 180
0.28 —
71.4
±9.14
0.135
—
—
0.175
0.160 0.205
0.140 —
0.250 —
7.3
—
8.1
—
Units
GHz
MHz
ms
ms
ms
ps
ps
ns
ps RMS
ps RMS
ps pk-pk
ps pk
ps pk-pk
ps pk
Notes:
1. Measured as time from valid V_DD and V_DD33 rails (90% of their value) to when the serial interface is ready to respond
to commands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz.
2. Jitter generation test conditions f_IN = 100 MHz, f_OUT = 156.25 MHz LVPECL.
3. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.
4. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the
feedback divider is integer.
5. Initiate a soft reset command to align the outputs to within +/- 100 ps.
6. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input
clock. The time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time.
14
Rev. 1.0