SI5341 Datasheet, PDF(34/56 Page) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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SI5341 Datasheet, PDF (34/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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Si5341/40

5.5.6. LVCMOS Output Impedance And Drive Strength Selection

Each LVCMOS driver has a configurable output impedance. It is highly recommended that the minimum output

impedance (strongest drive setting) is selected and a suitable series resistor (Rs) is chosen to match the trace

impedance.

Table 16. Nominal Output Impedance vs OUTx_CMOS_DRV (register)

CMOS_DRIVE_Selection

VDDO

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

3.3 V

38 ï

30 ï

22 ï

2.5 V

43 ï

35 ï

24 ï

1.8 V

46 ï

31 ï

*Note: Refer to the Si5341/40 Family Reference Manual for more information on register settings.

5.5.7. LVCMOS Output Signal Swing

The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output

driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.

5.5.8. LVCMOS Output Polarity

When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTx). By

default the clock on the OUTx pin is generated with complementary polarity with the clock on the OUTx pin. The

LVCMOS OUTx and OUTx outputs can also be generated in phase.

5.5.9. Output Enable/Disable

The OE pin provides a convenient method of disabling or enabling the output drivers. When the OE pin is held high

all outputs will be disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be

individually disabled through register control.

5.5.10. Output Driver State When Disabled

The disabled state of an output driver is configurable as: disable low or disable high.

5.5.11. Synchronous/Asynchronous Output Disable Feature

Outputs can be configured to disable synchronously or asynchronously. The default state is synchronous output

disable. In synchronous disable mode the output will wait until a clock period has completed before the driver is

disabled. This prevents unwanted runt pulses from occurring when disabling an output. In asynchronous disable

mode the output clock will disable immediately without waiting for the period to complete.

Rev. 1.0

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