SI5341 Datasheet, PDF (19/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 11. SPI Timing Specifications (3-Wire)
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
SCLK Frequency
SCLK Duty Cycle
SCLK Period
Delay Time, SCLK Fall to SDIO Turn-on
Delay Time, SCLK Fall to SDIO Next-bit
Delay Time, CS Rise to SDIO Tri-State
Setup Time, CS to SCLK
Hold Time, CS to SCLK Rise
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CS)
Symbol
Min
Typ
Max
Units
f_SPI
—
—
20
MHz
T_DC
40
—
60
%
T_C
50
—
—
ns
T_D1
—
12.5
20
ns
T_D2
—
10
15
ns
T_D3
—
10
15
ns
T_SU1
5
—
—
ns
T_H1
5
—
—
ns
T_SU2
5
—
—
ns
T_H2
5
—
—
ns
T_CS
2
—
—
T_C
SCLK
CS
SDIO
T_SU1
T_SU2 T_H2
T_C
T_H1
T_D1
T_D2
T_CS
T_D3
Figure 4. 3-Wire SPI Serial Interface Timing
Rev. 1.0
19