SI5341 Datasheet, PDF (7/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 3. Input Specifications
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Units
Differential or Single-Ended/LVCMOS — AC-Coupled (IN0/IN0, IN1/IN1, IN2/IN2, FB_IN/FB_IN)
Input Frequency Range
f_IN
Differential
10
—
750
Single-ended/LVCMOS 10
—
250
Input Voltage Swing⁵
V_IN
Differential AC Coupled 100
—
1800
fin < 250 MHz
MHz
mVpp_se
Differential AC Coupled 225
—
1800 mVpp_se
250 MHz < fin < 750 MHz
Slew Rate^{1, 2}
Single-ended AC Coupled 100
—
3600 mVpp_se
fin < 250 MHz
SR
400
—
—
V/µs
Duty Cycle
DC
40
—
60
%
Capacitance
C_IN
—
2
—
pF
DC-Coupled CMOS Input Buffer (IN0, IN1, IN2)⁴
Input Frequency
f_IN
Input Voltage
V_IL
V_IH
Slew Rate^{1, 2}
SR
10
—
250
–0.2 —
0.33
0.49 —
—
400
—
—
MHz
V
V
V/µs
Duty Cycle
DC
Clock Input
40
—
60
%
Minimum Pulse Width
PW
Pulse Input
1.6
—
—
ns
Input Resistance
R_IN
—
8
—
Differential or Single-Ended/LVCMOS Clock at XA/XB
Input Frequency Range
f_IN Frequency range for best 48
—
200
output
jitter performance
kΩ
MHz
10
—
200
MHz
Input Single-ended Voltage Swing V_{IN_SE}
365
—
2000 mVpp_se
Notes:
1. Imposed for jitter performance.
2. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20 = ((0.8 - 0.2) * V_{IN_Vpp_se}) / SR.
3. V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD.
4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended
LVCMOS inputs to IN0,1,2 it is required to ac-couple into the differential input buffer.
5. Voltage swing is specified as single-ended mVpp.
6. Contact Silicon Labs Technical Support for more details.
Rev. 1.0
7