SI5341 Datasheet, PDF (31/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
5.3.3. Input Selection (IN0, IN1, IN2, XA/XB)
The active clock input is selected using the IN_SEL[1:0] pins or by register control. A register bit determines input
selection as pin or register selectable. There are internal pull ups on the IN_SEL pins.
Table 15. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0]
0
0
0
1
1
0
1
1
Selected Input
IN0
IN1
IN2
XA/XB
5.4. Fault Monitoring
The Si5341/40 provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB,
FB_IN) and loss of lock (LOL) for the PLL. This is shown in Figure 13.
IN0
IN0
÷P₀
LOS0
IN1
IN1
÷P₁
LOS1
IN2
÷P₂
LOS2
IN2
XA
XB
FB_IN
FB_IN
OSC
LOSXAB
÷P_fb
LOSFB
Si5341/40
LOL
PD LPF
PLL
÷
Mn
Md
Figure 13. LOS and LOL Fault Monitors
5.4.1. Status Indicators
The state of the status monitors are accessible by reading registers through the serial interface or with dedicated
pin (LOL). Each of the status indicator register bits has a corresponding sticky bit in a separate register location.
Once a status bit is asserted its corresponding sticky bit (_FLG) will remain asserted until cleared. Writing a logic
zero to a sticky register bit clears its state.
5.4.2. Interrupt Pin (INTR)
An interrupt pin (INTR) indicates a change in state with any of the status registers. All status registers are maskable
to prevent assertion of the interrupt pin. The state of the INTR pin is reset by clearing the status registers.
Rev. 1.0
31