SI5341 Datasheet, PDF(47/56 Page) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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SI5341 Datasheet, PDF (47/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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Si5341/40

Table 18. Pin Descriptions (Continued)

Pin Name

VDDO0

VDDO1

VDDO2

VDDO3

VDDO4

VDDO5

VDDO6

VDDO7

VDDO8

VDDO9

GND PAD

Pin Number

Si5341 Si5340

Pin Type1

Function

Output Clock Supply Voltage 0â9

Supply voltage (3.3 V, 2.5 V, 1.8 V) for OUTx, OUTx outputs.

See the Si5341/40 Family Reference Manual for power supply fil-

tering recommendations.

Leave VDDO pins of unused output drivers unconnected. An

alternate option is to connect the VDDO pin to a power supply and

disable the output driver to minimize current consumption.

Ground Pad

This pad provides electrical and thermal connection to ground and

must be connected for proper operation. Use as many vias as

practical and keep the via length to an internal ground plan as

short as possible.

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input

pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings.

3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK

low.

Rev. 1.0

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