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SI5341 Datasheet, PDF (55/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR | |||
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DOCUMENT CHANGE LIST
Revision 0.9 to Revision 0.95
ï®ï Removed advanced product information
revision history.
ï®ï Updated Ordering Guide and changed
references to revision B
ï®ï Updated parametric Tables 2,3,5,6,7,8 to reflect
production characterization
ï®ï Updated terminology to align with ClockBuilder
Pro software
ï®ï Table 9: I2C data hold time specification
corrected to 100 ns from 5 µs
Revision 0.95 to Revision 1.0
ï®ï General updates to typos in Tables 2,3,4,5,8,11,
and 12.
ï®ï Changed Vin_diff minimum value in Table 3 to
be the same as Vin_se.
ï®ï Added crosstalk spec for Si5340 to Table 5.
ï®ï Changed the schematic for AC Test
Configuration in Table 7.
ï®ï Changed the PLL lock time in Table 8.
ï®ï Added a spec to Table 8 for the VCO frequency
range.
ï®ï Changed the "Delay Time Between Chip
Selects" to be 2.0 clock periods.
ï®ï Changed Note 2 in Table 12 as only 25 and 48â
54 Mhz crystals are supported.
ï®ï Changed the timing specs for I2C and SPI.
ï®ï Added a 1.0 µf bypass capacitor
recommendation to be consistent with the
reference manual.
ï®ï Updated output-to-output skew spec.
Si5341/40
Rev. 1.0
55
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