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SI5341 Datasheet, PDF (55/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 0.95
Removed advanced product information
revision history.
Updated Ordering Guide and changed
references to revision B
Updated parametric Tables 2,3,5,6,7,8 to reflect
production characterization
Updated terminology to align with ClockBuilder
Pro software
Table 9: I2C data hold time specification
corrected to 100 ns from 5 µs
Revision 0.95 to Revision 1.0
General updates to typos in Tables 2,3,4,5,8,11,
and 12.
Changed Vin_diff minimum value in Table 3 to
be the same as Vin_se.
Added crosstalk spec for Si5340 to Table 5.
Changed the schematic for AC Test
Configuration in Table 7.
Changed the PLL lock time in Table 8.
Added a spec to Table 8 for the VCO frequency
range.
Changed the "Delay Time Between Chip
Selects" to be 2.0 clock periods.
Changed Note 2 in Table 12 as only 25 and 48–
54 Mhz crystals are supported.
Changed the timing specs for I2C and SPI.
Added a 1.0 µf bypass capacitor
recommendation to be consistent with the
reference manual.
Updated output-to-output skew spec.
Si5341/40
Rev. 1.0
55