SI5341 Datasheet, PDF (46/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 18. Pin Descriptions (Continued)
Pin Name
FINC
IN_SEL0
IN_SEL1
RSVD
NC
Pin Number
Si5341 Si5340
48
—
Pin Type¹
Function
I
Frequency Increment Pin²
This pin is used to step-up the output frequency of a selected out-
put. The affected output and its frequency change step size is reg-
ister configurable. This pin is internally pulled low with a ~20 k
resistor and can be left unconnected when not in use.
3
3
4
37
I
Input Reference Select²
I
The IN_SEL[1:0] pins are used in the manual pin controlled mode
to select the active clock input as shown in Table 15. These pins
are internally pulled up with a ~20 k resistor to the voltage
selected by the IO_VDD_SEL bit and can be left unconnected
when not in use.
20
—
21
—
—
Reserved
—
These pins are connected to the die. Leave disconnected.
55
—
—
56
—
—
—
22
—
No Connect
These pins are not connected to the die. Leave disconnected.
Power
VDD
VDDA
VDDS
32
21
46
32
60
39
—
40
13
8
—
9
—
26
P
Core Supply Voltage
The device core operates from a 1.8 V supply. A 1.0 µf bypass
capacitor is recommended
P
Core Supply Voltage 3.3 V
P
This core supply pin requires a 3.3 V power source.
A 1.0 µf bypass capacitor is recommended.
P
Status Output Voltage
The voltage on this pin determines the V_OL/V_OH on LOL and
LOS_XAXB status output pins.
A 0.1 µf to 1.0 µf bypass capacitor is recommended.
Notes:
1. I = Input, O = Output, P = Power.
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input
pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings.
3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK
low.
46
Rev. 1.0