SI5341 Datasheet, PDF (29/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
5.2. Frequency Configuration
The phase-locked loop is fully contained and does not require external loop filter components to operate. Its
function is to phase lock to the selected input and provide a common reference to the MultiSynth high-performance
fractional dividers.
A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers. Additional
output integer dividers provide further frequency division by an even integer from 2 to (2^25)-2. The frequency
configuration of the device is programmed by setting the input dividers (P), the PLL feedback fractional divider (Mn/
Md), the MultiSynth fractional dividers (Nn/Nd), and the output integer dividers (R). Silicon Labs’ Clockbuilder Pro
configuration utility determines the optimum divider values for any desired input and output frequency plan.
5.3. Inputs
The Si5341/40 requires either an external crystal at its XA/XB pins or an external clock at XA/XB or IN0,1,2.
5.3.1. XA/XB Clock and Crystal Input
An internal crystal oscillator exists between pin XA and XB. When this oscillator is enabled, an external crystal
connected across these pins will oscillate and provide a clock input to the PLL. A crystal frequency of 25 MHz can
be used although crystals in the frequency range of 48 MHz to 54 MHz are recommended for best jitter
performance. Frequency offsets due to C_L mismatch can be adjusted using the frequency adjustment feature
which allows frequency adjustments of ±1000 ppm. The Si5341/40 Family Reference Manual provides additional
information on PCB layout recommendations for the crystal to ensure optimum jitter performance. Refer to
Table 12 for crystal specifications.
The Si5341/40 can also accommodate an external input clock instead of a crystal. This allows the use of crystal
oscillator (XO) instead of a XTAL. Selection between the external XTAL or input clock is controlled by register
configuration. The internal crystal load capacitors (C_L) are disabled in the input clock mode. Refer to Table 3 for the
input clock requirements at XAXB. Both a single-ended or a differential input clock can be connected to the XA/XB
pins as shown in Figure 11. A P_XAXB divider is available to accommodate external clock frequencies higher than
54 MHz.
Rev. 1.0
29