SI5341 Datasheet, PDF(15/56 Page) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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SI5341 Datasheet, PDF (15/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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Si5341/40

Table 8. Performance Characteristics (Continued)

(VDD = 1.8 V Â±5%, VDDA = 3.3 V Â±5%, TA = â40 to 85 Â°C)

Parameter

Jitter Generation

Locked to External XTAL

Symbol

JGEN

JPER

JCC

JPER

JCC

Test Condition

Min Typ

XTAL Frequency = 48 MHz

Integer Mode3

12 kHz to 20 MHz

â 0.090

Fractional/DCO Mode4

12 kHz to 20 MHz

â 0.120

Max

0.150

0.165

Derived from

integrated phase noise

â 0.150 â

â 0.270 â

N = 10, 000 cycles

7.3

Integer or Fractional Mode3,4 .

Measured in the time domain.

7.8

Performance is limited by the

noise floor of the equipment.

Units

ps RMS

ps pk-pk

ps pk

ps pk-pk

ps pk

XTAL Frequency = 25 MHz

JGEN

Integer Mode

12 kHz to 20 MHz

0.125 0.330 ps RMS

Fractional

12 kHz to 20 MHz

0.170 0.360 ps RMS

Notes:

1. Measured as time from valid VDD and VDD33 rails (90% of their value) to when the serial interface is ready to respond

to commands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz.

2. Jitter generation test conditions fIN = 100 MHz, fOUT = 156.25 MHz LVPECL.

3. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.

4. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the

feedback divider is integer.

5. Initiate a soft reset command to align the outputs to within +/- 100 ps.

6. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input

clock. The time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time.

Rev. 1.0

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