SI5341 Datasheet, PDF(33/56 Page) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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SI5341 Datasheet, PDF (33/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

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Si5341/40

5.5.3. Differential Output Modes

There are two selectable* differential output modes: Normal and Low Power. Each output can support a unique

mode. In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these

signaling standards.

ï® Differential Normal Mode: When an output driver is configured in normal mode, its output amplitude is

selectable as one of 7 settings ranging from ~130 mVpp_se to ~920 mVpp_se in increments of ~100 mV. See

Appendix A for additional information. The output impedance in the normal mode is 100 ïï differentialï®ï Any of

the terminations shown in Figure 14 are supported in this mode.

ï® Differential Low Power Mode: When an output driver is configured in low power mode, its output amplitude is

configurable as one of 7 settings ranging from ~200 mVpp_se to ~1600 mVpp_se in increments of ~200 mV.

When in Differential Low Power Mode, the output impedance of the driver is much greater than 100 ïï¬ï however

the signal integrity will still be optimum as long as the differential clock traces are properly terminated in their

characteristic impedance. Any of the terminations shown in Figure 14 are supported in this mode.

*Note: Not all amplitude levels are available for selection in the CBPro device configuration Wizard. Refer to Sections 5.9 and

5.10 for more information. See also Appendix A of the Si5341/40 Reference Manual.

5.5.4. Programmable Common Mode Voltage For Differential Outputs

The common mode voltage (VCM) for the differential Normal and Low Power modes are programmable so that

LVDS specifications can be met and for the best signal integrity with different supply voltages. When dc coupling

the output driver it is essential that the receiver should have a relatively high common mode impedance so that the

common mode current from the output driver is very small.

5.5.5. LVCMOS Output Terminations

LVCMOS outputs are typically dc-coupled as shown in Figure 15.

DC Coupled LVCMOS

VDDO = 3.3V, 2.5V, 1.8V

OUTx

3.3V, 2.5V, 1.8V

LVCMOS

Figure 15. LVCMOS Output Terminations

Rev. 1.0

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