SI5341 Datasheet, PDF (18/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 10. SPI Timing Specifications (4-Wire)
(V_DD = 1.8 V ±5%, V_DDA = 3.3V ±5%, T_A = –40 to 85 °C)
Parameter
SCLK Frequency
SCLK Duty Cycle
SCLK Period
Delay Time, SCLK Fall to SDO Active
Delay Time, SCLK Fall to SDO
Delay Time, CS Rise to SDO Tri-State
Setup Time, CS to SCLK
Hold Time, CS to SCLK Rise
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CS)
Symbol
Min
Typ
Max
Units
f_SPI
—
—
20
MHz
T_DC
40
—
60
%
T_C
50
—
—
ns
T_D1
—
12.5
18
ns
T_D2
—
10
15
ns
T_D3
—
10
15
ns
T_SU1
5
—
—
ns
T_H1
5
—
—
ns
T_SU2
5
—
—
ns
T_H2
5
—
—
ns
T_CS
2
—
—
T_C
SCLK
CS
SDI
SDO
TSU1
T_D1
T_C
TSU2
TH2
TD2
Figure 3. 4-Wire SPI Serial Interface Timing
T_H1
TCS
T_D3
18
Rev. 1.0