SI5341 Datasheet, PDF (32/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
5.5. Outputs
The Si5341 supports 10 differential output drivers which can be independently configured as differential or
LVCMOS. The Si5340 supports 4 output drivers independently configurable as differential or LVCMOS.
5.5.1. Output Signal Format
The differential output amplitude and common mode voltage are both fully programmable and compatible with a
wide variety of signal formats including LVDS and LVPECL. In addition to supporting differential signals, any of the
outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs, or
any combination of differential and single-ended outputs.
5.5.2. Differential Output Terminations
The differential output drivers support both ac-coupled and dc-coupled terminations as shown in Figure 14.
DC Coupled LVDS
VDDO = 3.3V, 2.5V, 1.8V
Si5341/40
OUTx
OUTx
50
100
50
AC Coupled LVDS/LVPECL
VDDO = 3.3V, 2.5V, 1.8V
50
OUTx
OUTx
100
50
Si5341/40
Internally
self-biased
DC Coupled LVCMOS
VDDO = 3.3V, 2.5V, 1.8V
50
OUTx
Rs
OUTx
Si5341/40
50
Rs
3.3V, 2.5V, 1.8V
LVCMOS
AC Coupled LVPECL/CML
VDDO = 3.3V, 2.5V
Si5341/40
OUTx
OUTx
VDD – 1.3V
50
50
50
50
AC Coupled HCSL
VDDO = 3.3V, 2.5V, 1.8V
Si5341/40
OUTx
OUTx
R1
50
50
R2
VDDRX
R1
R2
Standard
HCSL
Receiver
For VO_CMpt=ion0.137 V
VDD_RX
3.3 V
2.5 V
1.8 V
R1
R2
442 Ohms 56.2 Ohms
332 Ohms 59 Ohms
243 Ohms 63.4 Ohms
Figure 14. Supported Differential Output Terminations
32
Rev. 1.0