SI5341 Datasheet, PDF (43/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 18. Pin Descriptions (Continued)
Pin Name
Outputs
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6
OUT6
OUT7
OUT7
OUT8
OUT8
OUT9
OUT9
Pin Number
Pin Type¹
Si5341 Si5340
Function
24
20
23
19
28
25
27
24
31
31
30
30
35
36
34
35
38
—
37
—
42
—
41
—
45
—
44
—
51
—
50
—
54
—
53
—
59
—
58
—
O
Output Clocks
O
These output clocks support a programmable signal amplitude
when configured as a differential output. Desired output signal for-
O
mat is configurable using register control. Termination recommen-
O
dations are provided in "5.5.2. Differential Output Terminations"
on page 32 and "5.5.5. LVCMOS Output Terminations" on page
O
33. Unused outputs should be left unconnected.
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Notes:
1. I = Input, O = Output, P = Power.
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input
pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings.
3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK
low.
Rev. 1.0
43