SI5341 Datasheet, PDF (13/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 7. LVCMOS Clock Output Specifications (Continued)
(V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C)
Parameter
Symbol
Output Voltage Low^{1, 2, 3} V_OL
LVCMOS Rise and Fall
tr/tf
Times³
(20% to 80%)
Test Condition
Min
V_DDO = 3.3 V
OUTx_CMOS_DRV=1
I_OL = 10 mA
—
OUTx_CMOS_DRV=2
I_OL = 12 mA
—
OUTx_CMOS_DRV=3
I_OL = 17 mA
—
V_DDO = 2.5 V
OUTx_CMOS_DRV=1
I_OL = 6 mA
—
OUTx_CMOS_DRV=2
I_OL = 8 mA
—
OUTx_CMOS_DRV=3
I_OL = 11 mA
—
V_DDO = 1.8 V
OUTx_CMOS_DRV=2
I_OL = 4 mA
—
OUTx_CMOS_DRV=3
I_OL = 5 mA
—
VDDO = 3.3V
—
VDDO = 2.5 V
—
VDDO = 1.8 V
—
Typ Max Units
— V_DDO V
— ^{x 0.15}
—
— V_DDO V
— ^{x 0.15}
—
— V_DDO V
— ^{x 0.15}
420 550 ps
475 625 ps
525 705 ps
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer
to the Reference Manual for more details on register settings.
2. I_OL/I_OH is measured at V_OL/V_OH as shown in the dc test configuration.
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50  PCB trace. A 5 pF
capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
DC Test Configuration
Zs
V_OL/V_OH
I_OL/I_OH
IDDO
OUT
OUT
AC Test Configuration
Trace length 5 inches
499 
0.1 uF
50 
4.7 pF
56 
50 probe, scope
50 
499 
4.7 pF
0.1 uF
56 
50 probe, scope
Rev. 1.0
13