SI5341 Datasheet, PDF (45/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
Table 18. Pin Descriptions (Continued)
Pin Name
Pin Number
Pin Type¹
Si5341 Si5340
Function
Control/Status
INTR
12
33
O
Interrupt²
This pin is asserted low when a change in device status has
occurred. This interrupt has a push pull output and should be left
unconnected when not in use.
RST
6
17
I
Device Reset²
Active low input that performs power-on reset (POR) of the
device. Resets all internal logic to a known state and forces the
device registers to their default values. Clock outputs are disabled
during reset. This pin is internally pulled up with a ~20 k resistor
to the voltage selected by the IO_VDD_SEL bit.
OE
11
12
I
Output Enable²
This pin disables all outputs when held high. This pin is internally
pulled low and can be left unconnected when not in use.
LOL
47
—
O
Loss Of Lock²
This output pin indicates when the DSPLL is locked (high) or out-
of-lock (low). An external pull up or pull down is not needed.
—
27
O
Loss Of Lock
This output pin indicates when the DSPLL is locked (high) or out-
of-lock (low). An external pull up or pull down is not needed. The
voltage on the VDDS pin sets the VOH/VOL for this pin. See
Table 6.
LOS_XAXB —
28
O
Loss Of Signal
This output pin indicates a loss of signal at the XA/XB pins.
SYNC
5
—
I
Output Clock Synchronization²
An active low signal on this pin resets the output dividers for the
purpose of re-aligning the output clocks. For a tighter alignment of
the clocks, a soft reset should be applied. This pin is internally
pulled up with a ~20 k resistor to the voltage selected by the
IO_VDD_SEL bitand can be left unconnected when not in use.
FDEC
25
—
I
Frequency Decrement Pin²
This pin is used to step-down the output frequency of a selected
output. The affected output driver and its frequency change step
size is register configurable. This pin is internally pulled low with a
~20 k resistor and can be left unconnected when not in use.
Notes:
1. I = Input, O = Output, P = Power.
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input
pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings.
3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK
low.
Rev. 1.0
45