SI5341 Datasheet, PDF (36/56 Pages) Silicon Laboratories – LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR

Si5341/40
5.5.13. Zero Delay Mode
A zero delay mode is available for applications that require fixed and consistent minimum delay between the
selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through
software configuration and closing the loop externally as shown in Figure 17. This helps to cancel out the internal
delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the outputs can be fed
back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to
minimize the input-to-output delay. It is recommended to connect OUT9 (Si5341) or OUT3 (Si5340) to FB_IN for
external feedback. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A
differential external feedback path connection is necessary for best performance.
IN0
IN0
f_IN
IN1
IN1
IN2
IN2
IN_SEL[1:0]
f_FB = f_IN
FB_IN
FB_IN
÷ P0
÷ P1
÷ ^P2
Zero Delay
Mode
÷Pfb
Si5341
PLL
PD
÷
M_n
Md
LPF
MultiSynth
& Dividers
÷
N9n
N_9d
÷R₉
VDDO0
OUT0
OUT0
VDDO1
OUT1
OUT1
VDDO2
OUT2
OUT2
VDDO3
OUT3
OUT3
VDDO7
OUT7
OUT7
VDDO8
OUT8
OUT8
VDDO9
OUT9
OUT9
External Feedback Path
Figure 17. Si5341 Zero Delay Mode Setup
5.5.14. Sync Pin (Synchronizing R Dividers)
All the output R dividers are reset to the default NVM register state after a power-up or a hard reset. This ensures
consistent and repeatable phase alignment across all output drivers to within ±100 ps of the expected value from
the NVM download. Resetting the device using the RST pin or asserting the hard reset bit will have the same
result. The SYNC pin provides another method of re-aligning the R dividers without resetting the device, however,
the outputs will only align to within 50 ns when using the SYNC pin. This pin is positive edge triggered. Asserting
the sync register bit provides the same function as the SYNC pin. A soft reset will align the outputs to within
±100 ps of the expected value based upon the Nx_DELAY parameter.
5.5.15. Output Crosspoint
The output crosspoint allows any of the N dividers to connect to any of the clock outputs.
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Rev. 1.0