4509 Datasheet, PDF (77/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
INSTRUCTIONS
Each instruction is described as follows;
(1) Index list of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
SYMBOL
The symbols shown below are used in the following list of instruction
function and the machine instructions.
Symbol
A
B
Register A (4 bits)
Register B (4 bits)
Contents
Symbol
RPS
R1L
Contents
Prescaler reload register (8 bits)
Timer 1 reload register (8 bits)
DR
Register D (3 bits)
E
Register E (8 bits)
Q1
A/D control register Q1 (4 bits)
V1
Interrupt control register V1 (4 bits)
V2
Interrupt control register V2 (4 bits)
R1H
R2L
R2H
PS
T1
Timer 1 reload register (8 bits)
Timer 2 reload register (8 bits)
Timer 2 reload register (8 bits)
Prescaler
Timer 1
I1
Interrupt control register I1 (4 bits)
W1
Timer control register W1 (4 bits)
W2
Timer control register W2 (4 bits)
W5
Timer control register W5 (4 bits)
W6
Timer control register W6 (4 bits)
T2
T1F
T2F
WDF1
WEF
Timer 2
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
FR0
Port output structure control register FR0 (4 bits) INTE
Interrupt enable flag
FR1
Port output structure control register FR1 (4 bits) EXF0
External 0 interrupt request flag
FR2
Port output structure control register FR2 (4 bits) P
Power down flag
FR3
Port output structure control register FR3 (4 bits) ADF
A/D conversion completion flag
C1
Port output structure control register C1 (4 bits) SIOF
Serial interface transmit/receive completion flag
J1
Serial interface control register J1 (4 bits)
MR
Clock control register MR (4 bits)
D
Port D (6 bits)
K0
Key-on wakeup control register K0 (4 bits)
P0
K1
Key-on wakeup control register K1 (4 bits)
P1
K2
Key-on wakeup control register K2 (4 bits)
P2
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (2 bits)
L1
Key-on wakeup control register L1 (4 bits)
P3
Port P3 (2 bits)
PU0
Pull-up control register PU0 (4 bits)
PU1
Pull-up control register PU1 (4 bits)
x
Hexadecimal variable
PU2
Pull-up control register PU2 (4 bits)
X
Register X (4 bits)
Y
Register Y (4 bits)
y
Hexadecimal variable
z
Hexadecimal variable
p
Hexadecimal variable
Z
Register Z (2 bits)
n
Hexadecimal constant
DP
Data pointer (10 bits)
i
Hexadecimal constant
(It consists of registers X, Y, and Z)
PC
Program counter (14 bits)
PCH
High-order 7 bits of program counter
PCL
Low-order 7 bits of program counter
SK
Stack register (14 bits ✕ 8)
SP
Stack pointer (3 bits)
CY
Carry flag
j
A3A2A1A0
←
↔
?
()
—
M(DP)
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
Direction of data movement
Data exchange between a register and memory
Decision of state shown before “?”
Contents of registers and memories
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
a
Label indicating address a6 a5 a4 a3 a2 a1 a0
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p6 p5 p4 p3 p2 p1 p0
C
Hex. C + Hex. number x (also same for others)
+
x
Note : The 4509 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the
number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.
Rev.1.02 2006.12.22 page 77 of 140
REJ03B0147-0102