4509 Datasheet, PDF (47/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
RESET FUNCTION
System reset is performed by the followings:
• “L” level is applied to the RESET pin externally,
• System reset instruction (SRST) is executed,
• Reset occurs by watchdog timer,
• Reset occurs by built-in power-on reset (only for H version)
• Reset occurs by voltage drop detection circuit (only for H version)
Then when “H” level is applied to RESET pin, software starts from
address 0 in page 0.
(1) RESET pin input
System reset is performed certainly by applying “L” level to RESET
pin for 1 machine cycle or more when the following condition is sat-
isfied;
the value of supply voltage is the minimum value or more of the rec-
ommended operating conditions.
RESET
pin
(Note 2)
(Note 1)
Pull-up transistor
Internal reset signal
SRST instruction
Power-on reset circuit(Note 3)
Voltage drop detection circuit ^{(Note 3)}
Watchdog reset signal
WEF
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
3: These are equipped with only H version.
Fig. 40 Structure of reset pin and its peripherals
Reset input
1 machine cycle or more
RESET
0.3VDD
0.85VDD
Program starts
(address 0 in page 0)
(Note 1)
f(RING)
On-chip oscillator (internal oscillator) is
counted 120 to 144 times (Note 2).
Notes 1: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
2: It depends on the internal state at reset.
Fig. 41 RESET pin input waveform and reset release timing
Rev.1.02 2006.12.22 page 47 of 140
REJ03B0147-0102