4509 Datasheet, PDF (49/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
(4) Internal state at reset
Figure 43 shows internal state at reset (they are the same after sys-
tem is released from reset). The contents of timers, registers, flags
and RAM except shown in Figure 43 are undefined, so set the initial
value to them.
• Program counter (PC) ..............................................................................0......0......0.......0......0... 0
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) .................................................................................................. 0
• Power down flag (P) ............................................................................................................. 0
• External 0 interrupt request flag (EXF0) .............................................................................. 0
• Interrupt control register V1 ..................................................................................0.......0......0... 0
• Interrupt control register V2 ..................................................................................0.......0......0... 0
• Interrupt control register I1 ...................................................................................0.......0......0... 0
• Timer 1 interrupt request flag (T1F) ..................................................................................... 0
• Timer 2 interrupt request flag (T2F) ..................................................................................... 0
• Watchdog timer flags (WDF1, WDF2) .................................................................................. 0
• Watchdog timer enable flag (WEF) ...................................................................................... 1
• Timer control register PA ...................................................................................................... 0
• Timer control register W1 .....................................................................................0.......0......0... 0
• Timer control register W2 .....................................................................................0.......0......0... 0
• Timer control register W5 .....................................................................................0.......0......0... 0
• Timer control register W6 .....................................................................................0.......0......0... 0
• Clock control register MR .....................................................................................1.......1......0... 1
• Clock control register RG ..................................................................................................... 0
• Serial interface transmit/receive completion flag (SIOF) ..................................................... 0
• Serial interface control register J1 .......................................................................0.......0......0... 0
• Serial interface register SI ..........................................................✕.......✕.......✕......✕......✕.......✕......✕... ✕
• A/D conversion completion flag (ADF) ................................................................................. 0
• A/D control register Q1 .........................................................................................0.......0......0... 0
• Successive comparison register AD ..............................✕......✕......✕.......✕.......✕......✕......✕.......✕......✕... ✕
• Comparator register ....................................................................✕.......✕.......✕......✕......✕.......✕......✕... ✕
• Key-on wakeup control register K0 ......................................................................0.......0......0... 0
• Key-on wakeup control register K1 ......................................................................0.......0......0... 0
• Key-on wakeup control register K2 ......................................................................0.......0......0... 0
• Key-on wakeup control register L1 ......................................................................0.......0......0... 0
• Pull-up control register PU0 .................................................................................0.......0......0... 0
• Pull-up control register PU1 .................................................................................0.......0......0... 0
• Pull-up control register PU2 .................................................................................0.......0......0... 0
• Port output structure control register FR0 ...........................................................0.......0......0... 0
• Port output structure control register FR1 ...........................................................0.......0......0... 0
• Port output structure control register FR2 ...........................................................0.......0......0... 0
• Port output structure control register FR3 ...........................................................0.......0......0... 0
• Port output structure control register C1 ..............................................................0.......0......0... 0
• Carry flag (CY) ...................................................................................................................... 0
• Register A .............................................................................................................0.......0......0... 0
• Register B .............................................................................................................0.......0......0... 0
• Register D ....................................................................................................................✕......✕... ✕
• Register E ...................................................................................✕.......✕.......✕......✕......✕.......✕......✕... ✕
• Register X .............................................................................................................0.......0......0... 0
• Register Y .............................................................................................................0.......0......0... 0
• Register Z ..........................................................................................................................✕... ✕
• Stack pointer (SP) .......................................................................................................1......1... 1
• Operation source clock .......................................................... On-chip oscillator (operating)
• Ceramic resonator circuit ..................................................................................... Operating
• RC oscillation circuit ...................................................................................................... Stop
00000000
(Interrupt disabled)
(Interrupt disabled)
(Interrupt disabled)
(Prescaler stopped)
(Timer 1 stopped)
(Timer 2 stopped)
(On-chip oscillator operating)
(Serial interface port not selected)
“✕” represents undefined.
Fig. 43 Internal state at reset
Rev.1.02 2006.12.22 page 49 of 140
REJ03B0147-0102