4509 Datasheet, PDF (6/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
DEFINITION OF CLOCK AND CYCLE
q Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal os-
cillator.
q System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the register MR and register RG.
q Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one ma-
chine cycle.
q Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Table Selection of system clock
MR3
1
1
0
0
1
1
0
0
Register MR, RG
MR2 MR1 MR0
1
–
1
0
–
1
1
–
1
0
–
1
1
0
0
0
0
0
1
0
0
0
0
0
RG0
0
0
0
0
–
–
–
–
System clock
f(STCK) = f(RING)/8
f(STCK) = f(RING)/4
f(STCK) = f(RING)/2
f(STCK) = f(RING)
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
Operation mode
Internal frequency divided by 8 mode
Internal frequency divided by 4 mode
Internal frequency divided by 2 mode
Internal frequency through mode
High-speed frequency divided by 8 mode
High-speed frequency divided by 4 mode
High-speed frequency divided by 2 mode
High-speed through mode
Note: The internal frequency divided by 8 is selected after system is released from reset.
Rev.1.02 2006.12.22 page 6 of 140
REJ03B0147-0102