4509 Datasheet, PDF (14/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
FUNCTION BLOCK OPERATIONS
CPU
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit
data addition, comparison, AND operation, OR operation, and bit
manipulation.
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange,
and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Figure
2).
Carry flag CY can be set to “1” with the SC instruction and cleared to
“0” with the RC instruction.
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit data,
and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p, BLA
p, or BMLA p instruction is executed (Figure 4).
Also, when the TABP p instruction is executed at UPTF flag = “1”,
the high-order 2 bits of ROM reference data is stored to the low-or-
der 2 bits of register D, the high-order 1 bit of register D is “0”. When
the TABP p instruction is executed at UPTF flag = “0”, the contents
of register D remains unchanged. The UPTF flag is set to “1” with the
SUPT instruction and cleared to “0” with the RUPT instruction. The
initial value of UPTF flag is “0”.
Register D is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.
(CY)
(M(DP))
Addition
(A)
<Carry>
ALU
<Result>
Fig. 1 AMC instruction execution example
<Set>
<Clear>
SC instruction RC instruction
CY
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
Register B TAB instruction Register A
B3 B2 B1 B0
A3 A2 A1 A0
TEAB instruction
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
B3 B2 B1 B0
A3 A2 A1 A0
Register B TBA instruction Register A
Fig. 3 Registers A, B and register E
TABP p instruction
ROM
Specifying address
8
4
0
PCH
p6 p5 p4 p3 p2 p1 p0
PCL
DR2DR1DR0 A3 A2 A1 A0
Low-order 4bits
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
The contents of The contents of
High-order 2 bits
Register D (3)
value p
register D
register A
* Flag UPTF = 1;
High-order 2 bits of reference data is
transferred to the low-order 2 bits of register D.
“0” is stored to the high-order 1 bit of register D.
Flag UPTF = 0;
Data is not transferred to register D.
Fig. 4 TABP p instruction execution example
Rev.1.02 2006.12.22 page 14 of 140
REJ03B0147-0102