4509 Datasheet, PDF (41/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the
register Q1 to “1.”
Below, the operation at comparator mode is described.
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the
8-bit comparator register as a register for setting comparison volt-
ages. The contents of register B is stored in the high-order 4 bits of
the comparator register and the contents of register A is stored in the
low-order 4 bits of the comparator register with the TADAB instruc-
tion.
When changing from A/D conversion mode to comparator mode, the
result of A/D conversion (register AD) is undefined.
However, because the comparator register is separated from register
AD, the value is retained even when changing from comparator
mode to A/D conversion mode. Note that the comparator register
can be written and read at only comparator mode.
If the value in the comparator register is n, the logic value of com-
parison voltage Vref generated by the built-in DA converter can be
determined from the following formula:
Logic value of comparison voltage Vref
Vref = ^VDD ✕ n
256
n: The value of register AD (n = 0 to 255)
(12) Comparator operation start instruction
(ADST instruction)
In comparator mode, executing ADST starts the comparator operat-
ing.
The comparator stops 8 machine cycles after it has started (6 µs at
f(XIN) = 4.0 MHz in high-speed through mode). When the analog in-
put voltage is lower than the comparison voltage, the ADF flag is set
to “1.”
(13) Notes for the use of A/D conversion 1
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of reg-
ister AD is transferred to the high-order 2 bits of register A,
simultaneously, the low-order 2 bits of register A is “0.”
• Operating mode of A/D converter
Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
Clear the bit 2 of register V2 to “0” to change the operating mode
from the comparator mode to A/D conversion mode.
The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the compara-
tor mode to the A/D conversion mode. Accordingly, set a value to
the bit 3 of register Q1, and execute the SNZAD instruction to clear
the ADF flag.
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D
conversion, stores the results of comparing the analog input voltage
with the comparison voltage. When the analog input voltage is lower
than the comparison voltage, the ADF flag is set to “1.” The state of
ADF flag can be examined with the skip instruction (SNZAD). Use
the interrupt control register V2 to select the interrupt or the skip in-
struction.
The ADF flag is cleared to “0” when the interrupt occurs or when the
next instruction is skipped with the skip instruction.
ADST instruction
Comparison result
store flag(ADF)
DAC operation signal
Fig. 34 Comparator operation timing chart
8 machine cycles
Comparator operation completed.
(The value of ADF is determined)
Rev.1.02 2006.12.22 page 41 of 140
REJ03B0147-0102