4509 Datasheet, PDF (19/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
• Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request flag
for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt
enable/disable. Interrupts are enabled when INTE flag is set to “1”
with the EI instruction and disabled when INTE flag is cleared to “0”
with the DI instruction. When any interrupt occurs, the INTE flag is
automatically cleared to “0,” so that other interrupts are disabled un-
til the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2 to
select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and skip
instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corre-
sponding interrupt request flag is set to “1.” Each interrupt request
flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is sat-
isfied even if the interrupt is disabled by the INTE flag or its interrupt
enable bit. Once set, the interrupt request flag retains set until a
clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt dis-
able state is released, the interrupt priority level is as follows shown
in Table 3.
Table 3 Interrupt sources
Priority _{Interrupt name}
level
1 External 0 interrupt
2 Timer 1 interrupt
3 Timer 2 interrupt
4 A/D interrupt
5 Serial interface
interrupt
Activated condition
Level change of INT
pin
Timer 1 underflow
Timer 2 underflow
Completion of
A/D conversion
Completion of serial
interface transmit/
recieve
Interrupt
address
Address 0
in page 1
Address 4
in page 1
Address 6
in page 1
Address C
in page 1
Address E
in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip in-
struction
Interrupt name
Interrupt
request flag
Skip instruction
Interrupt
enable bit
External 0 interrupt
EXF0
SNZ0
V10
Timer 1 interrupt
T1F
SNZT1
V12
Timer 2 interrupt
T2F
SNZT2
V13
A/D interrupt
ADF
SNZAD
V22
Serial interface
interrupt
SIOF
SNZSI
V23
Table 5 Interrupt enable bit function
Interrupt enable bit Occurrence of interrupt
1
Enabled
0
Disabled
Skip instruction
Invalid
Valid
Rev.1.02 2006.12.22 page 19 of 140
REJ03B0147-0102