4509 Datasheet, PDF (27/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
On-chip oscillator
MR0
1
Division circuit
Divided by 8
Divided by 4
Divided by 2
MR3, MR2
11
10
01
00
System clock (STCK)
Internal clock
generating circuit
(divided by 3)
Instruction clock
(INSTCK)
Ceramic resonance
Multi-
XIN
plexer
0
RC oscillation
(CRCK)
(Note 1)
PA0
Prescaler (8)
ORCLK
(TABPS)
Reload register RPS (8)
(TPSAB)
(TPSAB)
(TPSAB)
Register B Register A
(TABPS)
INSTCK
Watchdog timer (16)
1 - - - - - - - - - - - - - - 16
(Note 2)
SQ
WDF1
WRST instruction R
RESET signal _{S Q}
(Note 4)
WEF
DWDT instruction R
+
WRST instruction (Note 3)
D Q Watchdog reset signal
T R RESET signal
Fig. 22 Timers structure (1)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Notes 1: When CRCK instruction is executed, RC oscillation is selected.
When CRCK instruction is not executed, ceramic resonance is selected.
2: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST
instruction is executed while flag WDF1 = “1”.
The next instruction is not skipped even when the WRST instruction is executed
while flag WDF1 = “0”.
3: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the
DWDT instruction and WRST instruction are executed continuously.
4: The WEF flag is set to “1” at system reset or RAM back-up mode.
Rev.1.02 2006.12.22 page 27 of 140
REJ03B0147-0102