4509 Datasheet, PDF (24/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
(2) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 interrupt.
Set the contents of this register through register A with the TI1A in-
struction. The TAI1 instruction can be used to transfer the contents
of register I1 to register A.
Table 8 External interrupt control register
Interrupt control register I1
I13
INT pin input control bit (Note 2)
at reset : 00002
at RAM back-up : state retained
0
INT pin input disabled
1
INT pin input enabled
R/W
TAI1/TI1A
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 2)
I11
INT pin edge detection circuit control bit
INT pin
I10
timer 1 control enable bit
Falling waveform (“L” level of INT pin is recognized with the SNZI0
0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
1
instruction)/“H” level
0
One-sided edge detected
1
Both edges detected
0
Disabled
1
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
Rev.1.02 2006.12.22 page 24 of 140
REJ03B0147-0102