4509 Datasheet, PDF (48/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
(2) Power-on reset (only for H version)
Reset can be automatically performed at power on (power-on reset)
by the built-in power-on reset circuit. When the built-in power-on re-
set circuit is used, set the time for the supply voltage to rise from 0 V
to the minimum voltage of recommended operating conditions to
100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and Vss at the shortest distance, and input “L” level to
RESET pin until the value of supply voltage reaches the minimum
operating voltage.
(3) System reset instruction (SRST)
By executing the SRST instruction, “L” level is output to RESET pin
and system reset is performed.
→ ←^{100 µs or less}
VDD
Power-on reset
circuit output
Reset
state
Internal reset signal
Power-on
Reset released
Reset state
Note: Keep the value of supply voltage to
the minimum value or more of the
recommended operating conditions.
Fig. 42 Power-on reset operation
Table 17 Port state at reset
Name
Function
State
D0, D1
D0, D1
High-impedance (Notes 1, 2)
D2/AIN4, D3/AIN5
D2, D3
High-impedance (Notes 1, 2, 3)
D4, D5
D4, D5
High-impedance (Notes 1, 2)
P00/SIN, P01/SOUT, P02/SCK P00, P01, P02 High-impedance (Notes 1, 2, 3)
P03
P03
High-impedance (Notes 1, 2, 3)
P10
P10
High-impedance (Notes 1, 2, 3)
P11/CNTR1
P11
High-impedance (Notes 1, 2, 3)
P12/CNTR0
P12
High-impedance (Notes 1, 2, 3)
P13/INT
P13
High-impedance (Notes 1, 2, 3)
P20/AIN0, P21/AIN1
P20, P21
High-impedance (Notes 1, 2, 3)
P30/AIN2, P31/AIN3
P30, P31
High-impedance (Notes 1, 2)
Notes 1: Output latch is set to “1.”
2: The output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
Rev.1.02 2006.12.22 page 48 of 140
REJ03B0147-0102