4509 Datasheet, PDF (51/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
RAM BACK-UP MODE
The 4509 Group has the RAM back-up mode.
When the POF instruction is executed continuously after the EPOF
instruction, system enters the RAM back-up state.
The POF instruction is equal to the NOP instruction when the EPOF
instruction is not executed before the POF instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM.
Table 19 shows the function and states retained at RAM back-up.
Figure 46 shows the state transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (return
from the normal reset state) can be identified by examining the state
of the power down flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters the
RAM back-up state by executing the EPOF instruction and POF in-
struction continuously, the CPU starts executing the program from
address 0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
• “L” level is applied to RESET pin,
• system reset (SRST) is performed,
• reset by watchdog timer is performed,
• reset by the built-in power-on reset circuit is performed (only for H
version), or
• reset by the voltage drop detection circuit is performed (only for H
version).
In this case, the P flag is “0.”
Table 19 Functions and states retained at RAM back-up
Function
RAM back-up
Program counter (PC), registers A, B,
✕
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
O
Interrupt control registers V1, V2
✕
Interrupt control register I1
O
Selected oscillation circuit (execution of CRCK)
O
Clock control register MR
✕
Clock control register RG
✕
Timer 1, Timer 2 function
Watchdog timer function
Timer control register PA
Timer control registers W1, W2
(Note 3)
✕ (Note 4)
✕
✕
Timer control registers W5, W6
O
Serial interface function
✕
Serial interface control register J1
O
A/D conversion function
✕
A/D control register Q1
O
Voltage drop detection circuit
(Note 5)
Port level
O
Key-on wakeup control registers K0 to K2, L1
O
Pull-up control registers PU0 to PU2
O
Port output structure control registers FR0 to FR3, C1
O
External interrupt request flag (EXF0)
✕
Timer interrupt request flags (T1F, T2F)
A/D conversion completion flag (ADF)
Serial interface transmit/receive completion flag
(SIOF)
Interrupt enable flag (INTE)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
(Note 3)
✕
✕
✕
✕ (Note 4)
✕ (Note 4)
Notes 1:“O” represents that the function can be retained, and “✕” represents
that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction,
and then set the system to be in the RAM back-up mode.
5: The voltage drop detection circuit is equipped with only H version.
In the RAM back-up mode, when the SVDE instruction is not ex-
ecuted, the voltage drop detection circuit is invalid, and when the
SVDE instruction is executed, the voltage drop detection circuit is
valid.
Rev.1.02 2006.12.22 page 51 of 140
REJ03B0147-0102