4509 Datasheet, PDF (71/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
Interrupt control register V2
V23
Serial interface interrupt enable bit
V22
A/D interrupt enable bit
V21
Not used
V20
Not used
at reset : 00002
at RAM back-up : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
0
This bit has no function, but read/write is enabled.
1
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
at RAM back-up : 00002
0 Interrupt disabled (SNZSI instruction is valid)
1 Interrupt enabled (SNZSI instruction is invalid)
0 Interrupt disabled (SNZAD instruction is valid)
1 Interrupt enabled (SNZAD instruction is invalid)
0
This bit has no function, but read/write is enabled.
1
0
This bit has no function, but read/write is enabled.
1
R/W
TAV1/TV1A
R/W
TAV2/TV2A
Interrupt control register I1
I13
INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 2)
I11
INT pin edge detection circuit control bit
INT pin
I10
timer 1 control enable bit
at reset : 00002
at RAM back-up : state retained
R/W
TAI1/TI1A
0
INT pin input disabled
1
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
1
instruction)/“H” level
0
One-sided edge detected
1
Both edges detected
0
Disabled
1
Enabled
MR3
MR2
MR1
MR0
Clock control register MR
at reset : 11012
at RAM back-up : 11012
MR3 MR2
Operation mode
0 0 Through mode (frequency not divided)
Operation mode selection bits
0 1 Frequency divided by 2 mode
1 0 Frequency divided by 4 mode
1 1 Frequency divided by 8 mode
Main clock f(XIN) control bit (Note 3)
0
Main clock (f(XIN)) oscillation enabled
1
Main clock (f(XIN)) oscillation stop
Operation source clock selection bit (Note 4)
0
1
Main clock (f(XIN))
On-chip oscillator clock (f(RING))
R/W
TAMR/TMRA
Clock control register RG
On-chip oscillator (f(RING)) control bit
RG0
(Note 5)
at reset : 02
at RAM back-up : 02
0
On-chip oscillator (f(RING)) oscillation enabled
1
On-chip oscillator (f(RING)) oscillation stop
W
TRGA
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
3: Main clock cannot be stopped when the main clock is selected for the operation source clock.
4: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabiliz-
ing wait time by software first and set the oscillation of the destination clock to be enabled.
5: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock.
Rev.1.02 2006.12.22 page 71 of 140
REJ03B0147-0102