4509 Datasheet, PDF (21/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are as-
signed to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
• Interrupt control register V2
The A/D interrupt enable bit and serial interface interrupt enable bit
are assigned to register V2. Set the contents of this register
through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
at RAM back-up : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
0
This bit has no function, but read/write is enabled.
1
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
R/W
TAV1/TV1A
Interrupt control register V2
at reset : 00002
at RAM back-up : 00002
0
V23
Serial interface interrupt enable bit
1
0
V22
A/D interrupt enable bit
1
0
V21
Not used
1
0
V20
Not used
1
Note: “R” represents read enabled, and “W” represents write enabled.
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
R/W
TAV2/TV2A
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable
bits (V10, V12, V13, V22, V23), and interrupt request flag are “1.” The
interrupt actually occurs 2 to 3 machine cycles after the cycle in
which all three conditions are satisfied. The interrupt occurs after 3
machine cycles only when the three interrupt conditions are satisfied
on execution of other than one-cycle instructions (Refer to Figure
16).
Rev.1.02 2006.12.22 page 21 of 140
REJ03B0147-0102