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4509 Datasheet, PDF (64/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER | |||
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4509 Group
10 P13/INT pin
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
⢠Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to â0â (refer to Figure 57â)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
â0â after executing at least one instruction (refer to Figure 57â).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 57â).
Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the fol-
lowing notes.
⢠Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to â0â (refer to Figure 59â)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
â0â after executing at least one instruction (refer to Figure 59â).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 59â).
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
; (âââ02)
; The SNZ0 instruction is valid ........... â
; (1âââ2)
; Control of INT pin input is changed
........................................................... â
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... â
â : these bits are not used here.
Fig. 57 External 0 interrupt program example-1
â Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to â0â, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
; (âââ02)
; The SNZ0 instruction is valid ........... â
; (1âââ2)
; Interrupt valid waveform is changed
........................................................... â
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... â
â : these bits are not used here.
Fig. 59 A/D conversion interrupt program example
⢠When the INT pin input is disabled (register I13 = â0â), set the key-
on wakeup of INT pin to be invalid (register L10 = â0â) before
system enters to the RAM back-up mode. (refer to Figure 58â).
LA 0
TI1A
DI
EPOF
POF2
; (âââ02)
; INT key-on wakeup disabled ........... â
; RAM back-up
â : these bits are not used here.
Fig. 58 External 0 interrupt program example-2
Rev.1.02 2006.12.22 page 64 of 140
REJ03B0147-0102
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