4509 Datasheet, PDF (129/142 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4509 Group
Skip condition
Datailed description
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– In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the high-order 4 bits (AD7–AD4) of comparator register to reg-
ister B, and the low-order 4 bits (AD3–AD0) of comparator register to register A.
(Q13: bit 3 of A/D control register Q1)
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V22 = 0: (ADF) = 1
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(P) = 1
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(WDF1) = 1
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– Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A.
“0” is stored to the least significant bit (A0) of register A.
– In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.
(Q13 = bit 3 of A/D control register Q1)
– Transfers the contents of A/D control register Q1 to register A.
– Transfers the contents of register A to A/D control register Q1.
– Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
– When V22 = 0 : Clears (0) to the ADF flag and skips the next instruction when A/D conversion completion
flag ADF is “1.” When the ADF flag is “0,” executes the next instruction.
When V22 = 1 : This instruction is equivalent to the NOP instruction. (V22: bit 2 of interrupt control register V2)
– No operation; Adds 1 to program counter value, and others remain unchanged.
– Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction.
Operations of all functions are stopped.
– Makes the immediate after POF instruction valid by executing the EPOF instruction.
– Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0.”
– Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
– Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1.” When the
WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when executing the
WRST instruction immediately after the DWDT instruction.
– System reset occurs.
– Clears (0) to the high-order bit reference enable flag UPTF.
– Sets (1) to the high-order bit reference enable flag UPTF.
– Validates the voltage drop detection circuit at RAM back-up (only for the H version).
Rev.1.02 2006.12.22 page 129 of 140
REJ03B0147-0102